Master-slave type flip-flop circuit

ABSTRACT

A master-slave type flip-flop circuit with first and second transmission gates receives an input pulse signal and an inverted input pulse signal at a data input terminal and an inverted data input terminal, respectively, and receives a clock signal at a common clock input terminal. A first data holding section includes first and second inverters and first and second resistors cross-connected between input and output terminals of the first and second inverters for receiving outputs of the first and second transmission gates at the input terminals of the first and second inverters. Third and fourth transmission gates receive outputs of the first and second inverters, respectively, of the data holding section and further receive an inverted clock signal at a common inverted clock input terminal. A second holding data section includes third and fourth inverters and third and fourth resistors cross-connected between input and output terminals of the third and fourth inverters fro receiving output of the third and fourth transmission gates at the input terminals of the third and fourth inverters, respectively, The flip-flop circuit is reduced in total number of inverters and hence in power consumption and further reduced in number of inverters on a signal transmission line to permit high-speed operation. Where first to fourth capacitors are connected in parallel to the first to fourth resistors, respectively, the speed of charging and discharging of gate capacity of the transmission gates can be raised to assure a higher maximum operating frequency.

FIELD OF THE INVENTION

This invention relates to a master-slave type flip-flop circuit, and more particularly to a master-slave type flip-flop circuit which is low in power consumption, high in operating speed and suitable for use with an optical communication system.

DESCRIPTION OF THE PRIOR ART

A maste-slave type flip-flop circuit is conventionally knwon which is constituted, for example, from a compound semiconductor (GaAs) IC (integrated circuit) wherein a GaAs MES FET (GaAs metal semiconductr field effect transistor) is employed as a logic gater element as disclosed, for example, in Japanese Patent Laid-Open Application No. 63-280509.

Referring to FIG. 1, there is shown in circuit diagram an exemplary one of such conventional master-slave type flip-flop circuits. The flip-circuit shown includes first to eight NOR circuits NOR₁ to NOR₈. The third and fourth NOR circuits NOR₃ and NOR₄ and the seventh and eight NOR circuits NOR₇ and NOR₈ each constitute a flip-flop circuit. The first and second NOR circuits NOR₁ and NOR₂ are connected to receive an input pulse signal and an inverted input pulse signal by way of a data input terminal D₁ and an inverted data input terminal D₂, respectively, and to receive a clock signal signal by way of a clock input terminal CLK₁. The fifth and sixth NOR circuits NOR₅ and NOR₆ are connected to receive outputs of the third and fourth NOR circuits NOR₃ and NOR₄, respectively, and to receive an inverted clock signal by way of an inverted clock input terminal CLK₂. Outputs of the seventh and eighth NOR circuits NOR₇ and NOR₈ are connected to an output terminal OUT₁ and an inverted output terminal OUT₂, respectively, of the master-slave type flip-flop circuit. It is to be noted that each of the NOR circuits NOR₁ to NOR₈ is constituted from a logic gate formed from, the example, a GaAs MES FET.

The master-slave type flip-flop circuit of FIG. 1 has a drawback in that a high speed operation cannot be anticipated because the first NOR circuit NOR₁, third NOR circuit NOR₃, fifth NOR circuit NOR₅ and seventh NOR circuit NOR₇ (or the second NOR circuit NOR₂, fourth NOR circuit NOR₄, sixth NOR circuit NOR₆ and eight NOR circuit NOR₈) are present on a signal transmission line and, if the gate delay time by one NOR circuit is, for example, 30 ps where each gate is formed from a GaAs MES FET, then the total delay time is 120 ps.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a master-slave type flip-flop circuit which has a reduced delay time.

In order to attain the object, according to the present invention, a master-slave type flip-flop circuit comprises first and second transmissiomn gates for receiving an input pulse signal and an inverted input pulse signal at a data input terminal and an inverted data input terminal, respectively, and for receiving a clock signal at a common clock input terminal, a first data holding section including first and second inverters and first and second resistors cross connected between input and output terminals of said first and second inveters for receiving outputs of said first and second transmission gates at the input terminals of said first and second inverters, respectively, third and fourth transmission gate for receiving outputs of said first and second inverters, respectively, of said first data holding section and for receiving an inverted clock signal at a common inverted clock input terminal, and a second data holding section including third and fourth inverters and third and fourth resistors cross connected between input and output terminals of said third and fourth inverters for receiving outputs of said third and fourth transmission gates at the input terminals of said third and fourth inverters, respectively. The flip-flop circuit is reduced in total number of inverters and hence in power consumption and further reduced in number of inverters on a signal transmission line to permit a high speed operation.

Each of the elements of the first to fourth transmission gates and elements of said first to fourth inverters may be formed from a GaAs field effect transistor, and first to fourth capacitors may be connected in parallel to said first to fourth resistors, respectively.

With the master-slave type flip-flop circuit, the number of inverters on a signal transmission line is reduced so that a high speed operation twice that of a conventional master-slave type flip-flop circuit can be achieved.

Further, as capacities between the gates and source of GaAs FETs of the first to fourth transmission gates are charged and discharged by way of the first and fourth capacitors connected in parallel to the first to fourth resistors, respectively, a high maximum operating frequency can be assured.

The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are denoted by like reference characters.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showin an exemplary one of conventional master-slave type flip-flop circuits;

FIG. 2 is a circuit diagram showing a master-slave type flip-flop circuit to which the present invention is applied;

FIG. 3 is a circuit diagram showing details of a data holding section of the master-slave type flip-flop circuit of FIG. 2;

FIG. 4 is a timing chart illustrating operation of the master-slave type flip-flop circuit of FIG. 2;

FIG. 5 is a circuit diagram of a data identifying circuit of an optical communication system to which a master-slave type flip-flop circuit according to the present invention is incorporated; and

FIG. 6 is a circuit diagram showing a modification to the master-slave type flip-flop circuit of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring first to FIG. 2, there is shown in circuit diagram a master-slave type flip-flop circuit according to which the present invention is applied. The master-slave type flip-flop circuit shown has a data input terminal D₁ and an inverted data input terminal D₂ and includes first to fourth transmission gates G₁ to G₄ each formed form, for example, a GaAs FET such as GaAs MES FET, a GaAs JFET (junction type field effect transistor) or a GaAs HEMT (high electron mobiltiy transistor), and first to fourth inverters INV₁ to INV₄. A clock signal S_(o1) is supplied to the first and second gates G₁ and G₂ by way of a clock input terminal CLK₁ while an inverted clock signal S_(o1) is supplied to the third and fourth gates G₃ and G₄ by way of an inverted clock input terminal CLK₂. The master-slave type flip-flop circuit further has an output terminal OUT₁ and an inverted output terminal OUT₂. The master-slave type flip-flop circuit further includes a first resistor R₁ connected betwen an input terminal P₁ of the first inverter INV₁ and an output terminal P₂ of the second inverter INV₂. A second resistor R₂ is connected between an input terminal P₃ of the second inverter INV₂ and an output terminal P₄ of the first inverter INV₁. A third resistor R₃ is connected between an input terminal of the third inverter INV₃ and the inverted output terminal OUT₂ of the fourth inverter INV₄. A fourth resistor R₄ is connected betwen an input terminal of the fourth inverter INV₄ and the output terminal OUT₁ of the third inverter INV₃. The master-slave type flip-flop circuit further includes a first data holding section Dr₁ composed of the first and second inverters INV₁ and INV₂ and the first and second resistor R₁ and R₂, and a second data holdin section D_(r2) composed of the third and fourth inverters INV₃ and INV₄ and the third and fourth resistors R₃ and R₄. Each of the first to fourth inverters INV₁ to INV₄ employs, as seen from FIG. 3 which shows a data holding section of a master-slave type flip-flop circuit of the present invention, a pair of GaAs FETs Q₁ and Q₂ such as, for example, GaAs MES FETs, GaAs JFETs or GaAs HEMTs as logic gate elements. It is to be noted that, while only the first data holding section D_(r1) is shown in FIG. 3, also the second data holding section D_(r2) has a substantially similar construction. In FIG. 3, reference characters RL₁ and RL₂ denote each a load resistor formed from a depletion type GaAs MES FET or the like, and V_(cc) a power source terminal.

Subsequently, operation of the master-slave type flip-flop circuit will be described with reference to FIG. 4.

When such an input pulse signal S₁ as seen from a waveform curve A shown in FIG. 4 is supplied to the data input terminal D₁ at the time t₀ and simultaneously another input signal similar to but inverted in phase from the input pulse signal S₁ is supplied to the inverted data input terminal D₂, the first data holding section D₁ is set at another time t₁ of a rising edge of a clock signal S_(c1) shown by a waveform curve B in FIG. 4 which is supplied to the first and second transmission gates G₁ and G₂ by way of the clock input terminal CLK₁. The first data holding section D_(r1) is reset at a further time t₃ after then. Consequently, such an output pulse signal S_(o1) as shown by a waveform curve D in FIG. 4 appears at the output terminal P₂ of the second inverter INV₂. Then, the second data holding section Dr₂ is set at a different time t₂ of a rising edge of an inverted clock signal S_(c2) shown by a waveform curve C in FIG. 4 whch is supplied to the inverted clock input terminal CLK₂, and is then reset at another time t₄. Consequently, such an output pulse signal S_(o2) as shown by a waveform curve E in FIG. 4 appears at the output terminal OUT₂ of the fourth inverter INV₄. When the second transmission gate G₂ is turned on at the time t₁, an output voltage of the second gate G₂ prevails over a feedback voltage supplied thereto from the output terminal P₄ of the first inverter INV₁ by way of the second resistor R₂ thereby to invert the second inverter INV₂ from a reset state into a set state. Then, a holding current is supplied to the second inverter INV₂ by way of the second resistor R₂ in order to hold the set state of the second inverter INV₂. On the other hand, when the fourth transmission gate G₄ is turned on at the time t₂, an output voltage of the fourth gate G₄ prevails over a feedback voltage supplied thereto from the output terminal OUT₁ of the third inventer INV₃ by way of the fourth resistor R₄ thereby to invert the fourth inverter INV₄ from a reset state into a set state. Then, a holding current is supplied to the fourth inverter INV₄ by way of the fourth resistor R₄ in order to hold the set state of the fourth inverter INV₄.

In this instance, if the delay time of each of the second and fourth inverter INV₂ and INV₄ is 30 ps and the delay time of each of the second and fourth transmission gates G₂ and G₄ is 5 ps, then the operating time of the master-slave type flip-flop circuit is 70 ps, which is about one half that of such conventional master-slave type flip-flop circuit as described hereinabove.

Subsequently, an exemplary application of a master-slave type flip-flop circuit according to the present invention will be described with reference to FIG. 5 which shows a data identifying circuit of an optical communication system.

The data identifying circuit shown in FIG. 5 includes an input amplifier A₁ which receives a data signal of an operating speed of, for example 2.4 Gb/s and supplies an input pulse signal S_(i) to a data input terminal D₁ and also supplies to another inverted data input terminal D₂ an inverted input pulse signal similar to but inverted in phase to the input pulse signal S_(i). Another input amplifier A₂ receives a clock signal having a higher frequency than the data signal and supplies a clock signal and an inverted clock signal to a clock input terminal CLK₁ cna an inverted clock input terminal CLK₂, respectively. Then, whether data supplied to the input amplifier A₁ is a mark (high level) or a space (low level) is detected in synchronism with the inverted clock signal at the inverted clock input terminal CLK₂, and a result of such detection is held in the fourth inverter INV₄. The data identifying circuit further includes a pair of output amplifiers A₃ and A₄.

Also with the data identifying circuit shown in FIG. 5, similar effects to those of the master-slave type flip-flop circuit shown in FIG. 2 can be anticipated.

Referring now to FIG. 6, there is shown in circuit diagram a modification to the master-slave type flip-flop circuit shown in FIG. 2. The modified master-slave type flip-flop circuit has a substantially similar construction to that of the master-slave type flip-flop circuit of FIG. 2 but additionally includes first to fourth capacitors C₁ to C₄ connected in parallel to the first to fourth resistors R₁ and R₄, respectively. Further, each of the first to fourth transmission gates G₁ to G₄ is formed froma GaAs FET.

In the modified master-slave type flip-flop circuit, charging and discharging of capacities C_(gs1) to C_(gs5) between the gates and sources of GaAs FETs forming the first to fourth transmission gates G₁ to G₄ take place by way of the first to fourth capacitors C₁ to C₄, respectively. Accordingly, possible deterioration of the first to fourth resistors R₁ to R₄ and the first to fourth capacitors by time constants is eliminated and the maximum operating frequency can be raised.

As apparent from the foregoing description, with a master-slave type flip-flop circuit of the present invention, as the number off inventers on a signal transmission line is reduce, a high speed operation twice that of a conventional master-slave type flip-flop circuit can be achieved.

Further, as capacities between the gates and sources of GaAs FETs of first to fourth transmission gates are charged and discharged by way of first and fourth capacitors connected in parallel to first to fourth resistors, respectively, there is an advantage that the maximum operating frequency can be raised.

Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereof without departing from the spirit and scope of the invention as set forth herein. 

What is claimed is:
 1. A master-slave type flip-flop circuit comprising:(a) first and second transmission gates for receiving an input pulse signal and an inverted input pulse signal at a data input terminal and an inverted data input terminal, respectively, and for receiving a clock signal at a first common clock input terminal; (b) a first data section including first and second inverters and first and second resistors cross-connected between input and output terminals of said first and second inverters for receiving outputs of said first and second transmission gates at the input terminal of said first and second inverters, respectively; (c) third and fourth transmission gates for receiving outputs of said first and second inverters of said first data holding section, respectively, and for receiving an inverted clock signal at a second common inverted clock input terminal; and (d) a second data holding section including third and fourth inverters and third and fourth resistors cross-connected between input and output terminals of said third and fourth inverters for receiving outputs of said third and fourth transmission gates at the input terminals of said third and fourth inverters, respectively.
 2. The master-slave type flip-flop circuit according to claim 1, further comprising first to fourth capacitors connected in parallel to said first to fourth resistors, respectively.
 3. The master-slave type flip-flop circuit according to claim 1, wherein each element of said first to fourth transmission gates and each element of said first to fourth inverters is formed from a GaAs field effect transistor.
 4. The master-slave type flip-flop circuit according to claim 3, wherein each of said elements of said first to fourth transmission gates and said elements of said first to fourth inverters is formed from a GaAs metal semi-conductor field effect transistor.
 5. The master-slave type flip-flop circuit according to claim 3, wherein each of said elements of said first to fourth transmission gates and said elements of said first to fourth inverters is formed from a GaAs junction type field effect transistor. 